In some types of memory devices, such as random access memories (RAM), a predetermined series of commands are received from a source attempting to access the memory device. Following receipt of each command, a set of operations related to each of the commands are performed subject to strict timing requirements with no overlap.
Unfortunately, the memory device has no control over when the commands are received, as the commands are generated by the external source. Thus, the timing constraints of the memory device are designed to match the timing constraints of the external sources compatible with the memory device in order to avoid errors.